1. Field of the Invention
In general, the present invention relates to the design of critical electronic circuits to be implemented on a chip or a printed circuit board. Especially, the present invention relates to a method for designing the layout of an electronic circuit, and a corresponding placement tool and computer program product.
2. Description of the Related Art
Using new technologies, the placement, which entails the wiring, has an increasing effect on signal delay of electronic circuitry. In order to receive accurate timing information early in the design phase, it is necessary to start physical placement of components as early as possible, even before designs are stable from the logic design point of view. Thus, new placing methods are required which can easily adapt design changes.
A layout representation of an electronic circuit comprises descriptions of the placement and wiring of all the components of the electronic circuit. An electronic circuit component can also be represented by a layout comprising planar geometric shapes, which span all needed, but hidden shapes in the layout editor to produce an electronic circuit in a chip manufacturing. A layout for an electronic circuit component needs to be placed in the layout for the electronic circuit.
As the layouts generated by conventional automatic placement tools cannot sufficiently fulfill all the design requirements, there is an increasing need to design critical electronic circuits of a chip in custom design style to receive the required performance. Besides performance, also additional design requirements such as the creation of dedicated regular structures or bit stacks can only be fulfilled by custom designs.
According to the state of the art designing electronic circuits in custom design style comprises the following steps:    1. Generating the layout representation for every component of the electronic circuit to be implemented. This can be done with a Layout Editor of the used CAD (Computer-Aided Design) system            a. completely manually by creating the correct planar geometrical shapes and all needed hidden shapes with the Layout Editor or        b. by using existing layout models from a library available in the CAD system or        c. by generating them with a program code used by the CAD system.            2. Placing every so generated layout for a component in the 2-dim. coordinate system of the Layout Editor by            a. “Drag and Drop”-moving the layouts for the components to that location the user wants it to be or        b. executing a program code that places the layouts for the components according to an algorithm.        In both cases every layout for a component receives absolute coordinates representing the location of the layout for the placed component.            3. Often, it is necessary to modify the layout of an electronic circuit to improve the performance of the corresponding electronic circuit. Those modifications are e.g. an exchange or displacement of the layout for a single component or modifications in shape and/or size of the layout for a single component. As consequence, an overlap and or empty space may occur between some of the layouts. Then, the locations of the layouts being affected by said modifications have to be aligned manually, because in most cases existing program algorithms do not meet the individual design requirements of critical electronic circuits.    4. Creating the wiring to connect the layouts electrically by            a. routing the connections with a Wire Editor manually or        b. running a Wiring-Router to do the job.            5. Finishing the custom circuit design according to the Design Rules for that particular chip technology.    6. Running all necessary Design Rule Checks.
The steps 2 and 3 create an inherent problem in the custom circuit design flow. For example, if the layout for a component is changed manually such that it overlaps the layout for another component, this will result in an electrical short and a malfunction of the logic function to be implemented by the electronic circuit. Another examples are manual layout changes for components that lead to unused chip area, and hence to larger and more expensive chips. The designer then needs to adapt the placement for all the components affected by this change manually. This is a time consuming and error prone task.